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Random Telegraph Signals in Semiconductor Devices

Eddy Simoen, Cor Claeys

Description

Following their first observation in small area silicon MOSFETs in 1984, random telegraph signals (RTS) were initially a purely scientific tool to study fundamental aspects of defects in semiconductor devices. However, as devices move to the nanometer scale, particularly memory devices and logic circuits, and in the development of alternatives to silicon MOSFETS, RTS have become an issue of major concern to the semiconductor industry. Moreover, following the move to the nanoscale, the devices will become more susceptible to single-trap random telegraph signal effects. It is clear that the successors to planar silicon transistors, including nanowire devices, tunnel field effect transistors, and carbon nanotubes are equally sensitive or even more so than current CMOS devices. It has become clear that the reliability of state-of-the-art and future CMOS technology nodes is dominated by RTS and single-trap phenomema, and so its understanding is of vital importance for the modelling and simulation of the operation and the expected lifetime of CMOS devices and circuits. It is the aim of this book to provide a comprehensive and up-to-date review of one of the most challenging issues facing the semiconductor industry, from the fundamentals of RTS to applied technology.

About Editors

Eddy Simoen is Senior Researcher at imec and Professor at Ghent University, Belgium. Cor Claeys is Director of Advanced Semiconductor Technologies at imec, and Professor at KU Leuven, Belgium.

Table of Contents

1) Introduction 2) RTS phenomenology a. RTS time constants i. Shockley-Read-Hall framework ii. Trap energy, capture barrier and location from SRH approach iii. Non SRH behavior: Coulomb blockade effects iv. Tunneling transitions b. RTS amplitude behavior c. RTS in the gate current of a MOS device d. RTS in the junction leakage current of a MOSFET e. Multiple and complex RTS 3) RTS modeling, simulation and parameter extraction a. Time constant modeling and simulation b. Extraction trap position from RTN time constants c. RTS amplitude modelling d. Atomistic numerical modeling of the RTS amplitude e. Novel measurement and analysis methods f. Ab initio modeling of RTS in gate dielectrics 4) Impact device processing and scaling on RTS a. Processing effects on RTS b. RTS in fin-type architectures c. Nanometric scaling aspects of RTS i. Scaling trend RTS amplitude ii. Silicon Gate-All-Around Nanowires iii. High-mobility channel materials iv. RTS in Tunnel FETs d. RTS in "beyond-silicon" devices i. Carbon Nanotubes (CNT) FETs ii. Other advanced devices 5) Operational and Reliability aspects of RTS a. Switching AC operation of RTS b. Impact of uniform and hot-carrier degradation c. BTI and RTS: oxide trapping? d. Statistical RTS measurement methods e. Device and circuit simulation of dynamic variability 6) RTS in memory and imager circuits a. RTS in Flash and SRAM cells b. RTS in DRAM and logic circuits c. RTS in novel ReRAM and PC memories d. RTS in CMOS Imagers and CCDs

Bibliographic

Hardback ISBN: 9780750312738

Ebook ISBN: 9780750312721

DOI: 10.1088/978-0-7503-1272-1

Publisher: Institute of Physics Publishing

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